In semiconductor device fabrication processes, different layers are formed on each other to create the desired integrated circuit device. In order that connections can be made for proper device operation, each layer should be properly aligned with another corresponding layer. In conventional alignment procedures, vernier marks were associated with each layer so that a fabrication operator could manually align each layer based on the position of corresponding vernier marks. However, imprecise human eye alignment techniques resulted in a great deal of alignment errors during device fabrication.
Scanning techniques were developed to increase the accuracy of layer alignment by measuring certain points associated with layers selected for alignment and comparing displacement of those points to ensure that the points fell within a certain tolerance. These scanning processes have historically used a single scan at each of several sites to determine and verify the alignment points of the wafer. These scanning processes also have difficulty finding the alignment points when there was signal distortion in the scanning zone due to extraneous material buildup during layer formation. Increasing the confidence level of the alignment method required making redundant, time consuming scans of the alignment points at each site, or of making single scans at ever increasing numbers of sites. Both approaches are unacceptable time consuming techniques for today's competitive market place. Therefore, it is desirable to have an aligning method with increased accuracy, less scanning time, and that overcomes material build up in the scanning zone as a result of layer formation.